Memory cells are used in the implementation of many types of electronic devices and integrated circuits, such as, but not limited to, erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memories. Memory cells are used to store the data and other information for these and other integrated circuits.
Non-volatile memory (NVM) cells generally comprise transistors with programmable threshold voltages. For example, a floating gate transistor or a split gate transistor has a threshold voltage (Vt) that is programmed or erased by charging or discharging a floating gate located between a control gate and a channel in the transistor. Data is written in such memory cells by charging or discharging the floating gates of the memory cells to achieve threshold voltages corresponding to the data.
The act of programming the cell involves charging the floating gate with electrons, which increases the threshold voltage Vt. The act of erasing the cell involves removing electrons from the floating gate, which decreases the threshold voltage Vt.
One type of non-volatile cell is a nitride, read only memory (NROM) cell, described in U.S. Pat. No. 6,011,725, the disclosure of which is incorporated herein by reference. Programming and erasing of NROM cells are also described in U.S. Pat. No. 6,011,725.
Unlike a floating gate cell, the NROM cell has two separated and separately chargeable areas. Each chargeable area defines one bit. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) stack underneath the gate. When programming a bit, channel hot electrons are injected into the nitride layer. This is generally accomplished by the application of a positive gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of programming required.
NROM cells may be single bit. Alternatively, they may have more than one bit, wherein two individual bits, a left-side bit and a right-side bit, are stored in physically different areas of the nitride layer. Each bit may be single level or multi-level (“MLC”), i.e., may be programmed to different voltage levels.
One procedure for programming bits in NROM cells with programming pulses is described in Applicant's copending U.S. patent application Ser. No. 09/730,586, entitled “Programming And Erasing Methods For An NROM Array”, the disclosure of which is incorporated herein by reference.
The application of pulses to operate (program or erase) the NROM array may pose a problem for mass storage or code flash applications. For example, in programming a mass storage array, a major requirement is a fast programming rate, in the range of at least 2 MB/sec. The channel hot electron injection (CHE) used for programming may require a relatively high programming current, e.g., approximately 100 μA per cell. In addition, each programming step may comprise switching and subsequent verification steps. These factors may limit the amount of cells that may be programmed in parallel to about 64 cells, for example.
Other complications that may hinder achieving fast, parallel programming rates include, among others, temperature dependence, cell length dependence (e.g., die to die and within a die), neighboring cell state dependence, second bit state dependence, and others. For example, FIG. 1 illustrates an effect of cell length on programming NROM cells. FIG. 1 illustrates the change in threshold voltage as a function of drain voltage used to program the cell. In the illustrated example, a first graph, denoted by the reference numeral 77, shows the change in threshold voltage as a function of drain voltage for a cell with a length of 0.5 microns. A second graph, denoted by the reference numeral 78, shows the change in threshold voltage as a function of drain voltage (Vd) for a cell with a length of 0.55 microns. It is seen that the slightly longer cell requires a higher drain voltage to achieve the same change in threshold voltage as the shorter cell.
As another example, FIG. 2 illustrates an effect of temperature on programming NROM cells. FIG. 2 illustrates the change in threshold voltage as a function of drain voltage (Vd) used to program the cell. In the illustrated example, a first graph, denoted by the reference numeral 79, shows the change in threshold voltage as a function of drain voltage in an ambient of 20° C. A second graph, denoted by the reference numeral 80, shows the change in threshold voltage as a function of drain voltage in an ambient of 85° C. It is seen that the warmer ambient requires a higher drain voltage to achieve the same change in threshold voltage as the cooler ambient.
Determination of programming pulses is also complicated by the fact that the cell parameters and operating conditions are usually initially unknown. Utilizing large programming pulse steps may reduce the total amount of programming pulses required to program the array. However, this may be disadvantageous because it may result in a wide and varied distribution of threshold voltages in the programmed cells of the array, which may reduce product reliability.
Alternatively, accurate verification of the cell threshold voltage and comparison of the threshold voltage to a variety of references may reduce the amount of programming pulses and provide faster convergence to the desired programmed threshold voltage level. However, such a method may incur a substantial overhead in the form of multiple verify pulses (e.g., one per reference), which is an undesirable time penalty, or may require an intricate parallel reference design, which is an undesirable chip area penalty.